1. Field of the Disclosure
The disclosure relates to a Faraday Cage surrounding semiconductor microchips, photovoltaic cells, and/or other micro and/or nano devices combined with the applicant's prior internal sipe inventions, including at least one compartment surrounded by at least one internal sipe, such as a slit. More specifically, a Faraday Cage coincides with an outer compartment, which forms one surface of a sipe surrounding an inner compartment including a personal computer microchip and/or a photovoltaic cell and/or a fuel cell and/or a battery.
The disclosure also relates to a semiconductor wafer, such as silicon, containing a multitude of microchips, such as with one or more core microprocessors. Instead of separating the microchips into separate dies in the conventional process, the entire semiconductor wafer is used essentially intact as a computer. More specifically, interconnects can be added to the printed circuit architecture of the wafer to connect the wafer microchips to other wafer microchips and/or other components on the wafer or external to it. Still more specifically, each microchip can be a complete system on a chip (SoC). Even more specifically, the semiconductor wafer can be used with other conventional interface devices for power and data, including wireless such as radio and/or optic, and/or wired such as fiber optic and/or electric, including for each SoC microchip on the wafer. In another specific embodiment, two or more semiconductor wafers can be stacked in vertical layers; for example, with a first wafer including microprocessors or cores; a second wafer including random access memory or RAM; and a third wafer including other components; each SoC microchip, in this example, can have one or more components on each of the three wafers.
The disclosure also relates to the semiconductor wafer including one or more of the applicant's prior internal sipe inventions, with an outer compartment having an internal sipe.
The disclosure also relates to the semiconductor wafer being surrounded by one or more Faraday Cages integrated into the internal sipe invention.
2. Brief Description of the Prior Art
Faraday Cage surrounding semiconductor microchips, photovoltaic cells, and/or other micro and/or nano devices, are described by the applicant in his U.S. application Ser. No. 10/802,049 filed Mar. 17, 2004, and published as Pub. No. US 2004/0215931 A1 on Oct. 28, 2004.
The applicant's prior internal footwear sipe inventions, including at least one compartment surrounded by at least one internal sipe, such as a slit, are described by the applicant in his U.S. patent application Ser. No. 11/802,930, filed May 25, 2007 and published as Pub. No. US 2008/0086916 A1 on Apr. 17, 2008, as well as in several earlier U.S. applications filed by the applicant.
Existing semiconductor wafers, currently up to 300 mm in diameter, are always cut into a large number of separate dies, with one microchip formed into a package from each flaw-free die cut from the semiconductor wafer; some dies are inherently defective and are discarded. A typical semiconductor wafer is shown in the applicant's U.S. application Ser. No. 10/684,657 filed Oct. 15, 2003.
As described in Wikipedia, “wafer scale integration” (WSI) is a yet-unused system of building very-large integrated circuit networks that use an entire silicon wafer to produce a single “super-chip.”Through a combination of large size and reduced packaging, WSI could lead to dramatically reduced costs for some systems, notably massively parallel supercomputers.
Many companies including TI and ITT attempted to develop “wafer scale integration” (WSI) production systems in the 1970's and ‘80’s, but all failed and no products were released. Further attempts at WSI appear to be largely abandoned for decades.
One critical problem that has not been overcome is that of inherent flaws in semiconductor wafers. It has been an ongoing goal to develop methods to handle faulty areas of the wafers through logic, as opposed to sawing them out of the wafer. Generally, this approach uses a grid pattern of sub-circuits and “rewires” around the damaged areas using appropriate logic.
The overwhelming difficulty of this approach is illustrated by the history of famous computer pioneer Gene Amdahl, who attempted to develop WSI as a method of making a supercomputer, starting Trilogy Systems in 1980 and garnering investments from Groupe Bull, Sperry Rand, and Digital Equipment Corporation, who (along with others) provided as estimated $230 million in financing. The design called for a 2.5″ square chip with 1200 pins on the bottom. After burning through about one third of the capital with nothing to show for it, Amdahl eventually declared the idea would only work with a 99.99% yield, which would not happen for 100 years. There were several subsequent efforts in the 1980's, but none successful.
Another well-known problem is the field of wafer-scale integration technology is the impact of thermal expansion on external connectivity. More specifically, when a WSI microelectronic complex is connected to a circuit board by thousands of, for example, connectors positioned between the microelectronic complex and the circuit board, these connectors can be damaged due to the different rates of thermal expansion experience by the surfaces of the microelectronic comples and circuit board.
Taking for example a finished silicon wafer, packaged in a material such as ceramic, the wafer typically expands at a rate of 3 ppm/C. In contrast, the material of the circuit board typically expands at a rate of 20-40 ppm/C. Thus, as the two materials heat up, the two surfaces will expand at different rates, potentially damaging many of the connectors distributed between the wafer and the circuit board. See Norman, et al., U.S. Pat. No. 7,279,787.
The present disclosure solves these longstanding problems with existing technology.